The present disclosure relates to power detectors detecting power and outputting signals.
In general, a power detector detecting power based on a predetermined voltage is used as a reset signal generator for a calculator in a semiconductor integrated circuit. When a power supply voltage is lower than or equal to a predetermined voltage Vo, a power detection signal, which indicates that power is undetected, is generally output to stop the calculator. On the other hand, when the power supply voltage is higher than the predetermined voltage Vo, a power detection signal, which indicates that power is detected, is output to operate the calculator, thereby operating the semiconductor integrated circuit.
The configuration of a power detector will be described.
A power detector includes, as shown in FIG. 8, a power voltage divider 11 and a comparator 14. The power voltage divider 11 linearly divides a power supply voltage using two resistors arranged in series between a power supply terminal and a ground terminal, and outputs a signal of an output voltage 12, which is the voltage at the time of division. The comparator 14 compares the output voltage 12 of the power voltage divider 11 to a reference voltage 13.
The comparator 14 has, for example, a configuration shown in FIG. 10. Specifically, the comparator 14 includes two MOS transistors 20 and 21, which have equal threshold voltages, a current supply 22, and a current minor 23, which is a semiconductor element. In the two MOS transistors 20 and 21, gates are coupled to inputs of the comparator 14, sources are commonly coupled to the current supply 22, and drains are coupled to the current minor 23. A drain 24 of one of the MOS transistors is coupled to an inverter 25. Then, an output 26 of the inverter 25 is the output of the comparator 14. The comparator 14 inverts the output of the inverter 25 when gate voltages of the two MOS transistors 20 and 21 are equal.
The operation of the power detector shown in FIG. 8 will be described.
In FIG. 8, the output voltage 12 of the power voltage divider 11 is a voltage obtained by dividing the power supply voltage with the resistors, and thus changes in proportion to the power supply voltage.
On the other hand, the reference voltage 13 is always fixed to the output voltage 12 of the power voltage divider 11 at the time when the power supply voltage is the predetermined voltage Vo, and is always constant regardless of the power supply voltage.
The comparator 14 receives the output voltage 12 of the power voltage divider 11 and the reference voltage 13, and inverts the power detection signal output from the comparator 14 when the two inputs are equal.
In FIG. 9, based on the comparison result of the comparator 14, when the output voltage 12 of the power voltage divider 11 is lower than or equal to the reference voltage 13, the comparator 14 generally regards the power supply voltage as being lower than or equal to the predetermined voltage Vo, and outputs a power detection signal indicating that the power supply is undetected (a low level in FIG. 9). When the output voltage 12 of the power voltage divider 11 is higher than the reference voltage 13, the comparator 14 regards the power supply voltage as being higher than the predetermined voltage Vo, and outputs a power detection signal 15 indicating that the power supply is detected (a high level in FIG. 9).
In the power detector operating as described above, the comparator 14 receives the voltage 12 changing in proportional to the power supply voltage at one input, and the constant reference voltage 13 at the other input. This causes a difference in bias application between the inputs of the comparator 14.
An MOS transistor has the problem of bias temperature (BT) degradation. BT degradation is fluctuations in the threshold voltage of an MOS transistor caused by applying positive or negative bias to the gate of the MOS transistor. Moreover, it is known that the amount of fluctuations changes depending on the temperature or the time for applying bias.
An MOS transistor, in which BT degradation occurs, influences the characteristics of an analog circuit. For example, the characteristics of the comparator 14 of inverting an output when input voltages are equal are on the assumption that the threshold voltages of the two MOS transistors 20 and 21 are equal.
However, a difference in bias application arises between the inputs of the comparator 14 in the power detector, thereby causing a difference in the amount of fluctuations in the threshold voltages due to BT degradation in the two MOS transistors 20 and 21, of which the gates are coupled to the inputs. This causes a difference in threshold voltage between the two MOS transistors 20 and 21. Thus, the comparator 14 inverts the output when the input signals are not equal, i.e., the predetermined voltage Vo fluctuates, at which a power voltage is to be detected.
Therefore, BT degradation reduces the power detection accuracy of the power detector.
As a known measure against the problem, for example, Japanese Patent Publication No. 2004-172796 (e.g., page 1, FIG. 2, etc.) suggest clamping the gates of MOS transistors to be protected from BT degradation to the same potential as the sources to prevent BT degradation when a circuit is inactive. FIG. 11 illustrates this configuration. In the drawing, MOS transistors 30 and 31 are to be protected from BT degradation. When the circuit is inactive, semiconductor elements 32 and 33 are powered on, and the gates and sources of the MOS transistors 30 and 31 are set to the same potential.